Fix overflowing add codegen, plus other fixes based on test output

[calc84maniac]

16-bit and 24-bit overflowing add now correctly generates ADC instead of ADD to obtain the overflow flag output. Additionally, the code generation for overflowing and extended add/sub has been updated to avoid performing the calculation twice when both the value and flag outputs are used.

In some cases, condition folding would generate fallback code even when the caller had its own fallback implementation, causing redundant instruction output. This has also been fixed by adding a parameter to indicate no fallback should be emitted when condition folding fails.

While looking at test output, I also identified and fixed the following issues:

• Implementations of the G_EXTRACT and G_INSERT opcodes were emitting 16-bit memory operations in 24-bit mode, when it should have been using 24-bit operations or 8-bit pseudo operations. This has been fixed to use 24-bit operations on loads (which are from stack slots and safe to overrun by one byte), pseudo 8-bit operations on stores for inserted subregs, and 24-bit operations for stores of a full 16-bit register (increasing the stack slot size if needed). Though, in most cases, extract/insert for full 16-bit registers will use direct subregister operations rather than stack slots in the first place.
• Fixed excessive code generation for G_MERGE_VALUES with s1 source operands, which was behavior introduced in v17. In many cases, the majority of the s1 source operands were constant or undef, intended for zero-ext or any-ext. So, to fix this issue, G_MERGE_VALUES has been optimized to account for constant or undef inputs, as well as minimize the total number of bits shifted.